Design of a highly reconfigurable interconnect for array processors

Diierent interconnection topologies have diierent desirable properties and diierent algorithms run best on diier-ent networks. If the network topology is reconngurable, it can be tailored to suit the particular algorithm being executed. Reconngurability of processor arrays is also important from fault-tolerance point of view. An array processor that is programmable by the user any number of times to yield a diierent topology or to isolate faults is envisaged in this paper. The system has a host or controller that broadcasts a command to the interconnect to conngure itself into a particular fashion. The interconnect uses static-RAM programming technology and can be programmed to different conngurations by sending a diierent set of bits to the connguration RAM in the interconnect. We present three designs reconngurable into array, ring, mesh, or Il-liac mesh topologies. The rst design is reconngurable to diierent topologies, but provides no redundancy or fault tolerance. The second and third designs are capable of graceful degradation by eliminating faulty elements.